A complementary metal-oxide semiconductor (CMOS) imaging sensor (CIS) is an integrated circuit (IC) device used to convert a light intensity pattern into electric digital signals. In some cases, a CIS is a two dimensional array of photodiodes with accompanying CMOS logic for signal processing. Each individual photodiode with processing CMOS logic is referred to a pixel. In some cases, a CIS has 1,000,000 or more pixels.
A CIS is commonly fabricated on n/n++ or p/p++ wafers. As an example, in some cases, thin lightly doped n-type or p-type epitaxial layers (e.g., 3-5 μm layers each having a dopant concentration of 1×1014 to 1×1015 cm−3) are grown on a highly doped n++ or p++ substrate (e.g., a substrate having a dopant concentration of 1×1018 to 1×1020 cm−3). A CIS is formed on the epitaxial layers, a region often referred to as the device active area. Performance of the CIS is influenced, at least in part, by properties of this active area.
The highly doped substrates (often referred to as handles) provide mechanical support for the active area during the CIS fabrication process. In some cases, the substrate also reduces the occurrence of cross-talk in a CIS. For example, the substrate can reduce the cross-talk that results when minority carriers generated underneath one pixel in response to red light reach adjacent pixels of the CIS.
A CIS can be arranged according to a variety of different configurations. For example, a CIS can be arranged as a front side illuminated (FSI) CIS, or as a back side illuminated (BSI) CIS. Here, the “front” side refers to the side of the wafer on which the IC pixel structures are fabricated. In some cases, to make a BSI CIS, a CIS wafer first undergoes CIS processing on its front side. The CIS wafer is then bonded along its front side to a wafer carrier, and its backside is thinned (e.g., by a few μm) until all of its n++ or p++ substrate is removed. The surface of the CIS wafer is then passivated and covered with an antireflection coating, and color filters are fabricated on its back side. During use, a light image is projected on the back side of the CIS wafer, and the CIS converts the light image into electric digital signals.
Light from an image projected on a CIS having photon energy larger than the silicon band gap is primarily absorbed in the CIS active area. This absorption generates electron and hole pairs, resulting in photocurrent. These photo-generated minority carriers are then collected by a p-n junction at this location. The number of photo-generated minority carriers is proportional to the number of photons that are absorbed in the CIS active area, and varies according to the intensity of light. Thus, the intensity of light incident upon the CIS active area can be deduced based on the magnitude of the generated photocurrent. In practice, it is often desirable for each of the pixels of a CIS to generate identical or substantially similar photocurrent in response to uniform, low level illumination. Otherwise, pixels having lower or higher photocurrent (e.g., “defective” pixels) might result in bright or dark spots in the resulting image.
In some cases, localized crystallographic defects and heavy metal contaminations could increase or decrease photocurrent from a given pixel, resulting in an image having bright spots or dark spots at low illumination levels. When present in a space charge region of the p-n junctions, these defects act as generation centers for minority carriers. This results in an increase in the dark current of these pixels, and if the defect is sufficiently severe, will result in white or bright spots in the resulting image. When present outside of the space charge region of p-n junctions, these defects act as recombination centers for minority carriers. This results in a decrease in the amount of photocurrent collected by the junctions, and if the defect is sufficiently severe, will result in as dark spots in the resulting image at low illumination levels.
Localized crystallographic defects or heavy metal contaminations can potentially be introduced at any step during the fabrication process of a CIS. Thus, to improve and control the fabrication process of a CIS, it is important to quickly identify processing steps that are introducing these defects.